Carrier leakage suppression and prevention of modulation accuracy deterioration are essential items for ensuring communication quality and for regulatory compliance in an orthogonal demodulator and a radio transmitter that use the orthogonal modulator. In recent years, with an increase in the speed of communication, a demanded performance level has got higher. However, due to circuit configuration constraints caused by a direct conversion architecture and a lower voltage of a process, the performance items described at the beginning of this paragraph rather tend to deteriorate. Accordingly, a certain compensation system needs to be included in an orthogonal modulator in order to satisfy performance requirement. Though a lot of compensation systems have been proposed so far, it is one of ideals not to add unnecessary hardware or the like so as to perform compensation. The conventional systems have a lot of improvements to be made in that respect.
A carrier leakage corresponds to a direct-current offset (DC offset) normalized by input level to the modulator. Among elements that affect modulation accuracy are the carrier leakage, a variation of levels between quadrature components (a type of IQ mismatch) normalized by input level to the modulator, and orthogonality of local signals input to the demodulator, or a variation of an amplitude and a variation of a phase difference (a type of IQ mismatch).
FIG. 28 is a diagram showing an example of a typical configuration of a signal compensation system of a related art.
When a compensating operation is performed, a test signal from a test signal generation unit is selected by a switch (SW). The test signal is supplied to a baseband port of an orthogonal modulator. An envelope detector detects the amplitude of an output of the orthogonal modulator. Then, the detected amplitude of the output is converted to a digital signal by an AD converter and is then supplied to a control unit. The orthogonal modulator includes mixers (MIXs) and an adder. The mixers (MIXs) multiply output signals of DA converters (D/A) by locally oscillated signals LO(I) and LO(Q) (with a phase difference of 90 degrees between the locally oscillated signals LO(Q) and LO(I)), respectively. The DA converters (D/A) convert I and Q components (of the digital signal) to analog signals, respectively. The adder adds the multiplied signals of the I and Q components.
FIG. 29 shows a test signal typically used in the configuration of FIG. 28 or the like. A cosine wave is supplied to an I side, while a sine wave is supplied to a Q side.
FIG. 30 shows a constellation when an RF/analog section of the modulator is ideal. A perfect circle having its center located at the point of origin is drawn. In a time domain of an output of the modulator, a sine wave having a constant envelope is obtained. FIG. 31 is a constellation when there is a DC offset. The center of the circle is shifted from the point of origin. For this reason, the envelope of an output of the modulator increases or decreases with time.
FIGS. 32 and 33 show constellations in respective cases where there is an IQ amplitude mismatch and where there is an IQ phase mismatch. As is expected, the envelope of an output of the modulator increases or decreases with time in each case. By comparing the cycle and phase of each of these envelopes that increases and decreases with the phase and frequency of the test signal, it is known which offset/mismatch is present in what amount. Then, a control signal for compensating for the offset/mismatch can be generated. The signal thus generated is supplied to a DC offset/IQ mismatch compensation unit. In performing communication, a transmission baseband signal generation unit is selected by the switch. A signal sent out from the transmission baseband signal generation unit is supplied to the DC offset/IQ mismatch compensation unit in which compensation information has been already set. Then, a resulting signal is then subject to DA conversion and supplied to the baseband port of the orthogonal modulator.
Patent Document 1 describes a method of calibrating an IQ phase error using only two points in first to fourth quadrants in an orthogonal modulator, as the signal compensation technique described above. Thus, a test signal is simplified.
Patent Document 2 discloses a method in which a sine-wave test signal is provided to a baseband input of a modulator, thereby performing calibration.
Patent Document 3 discloses a method of attempting to improve accuracy of a modulator, based on a signal obtained by frequency converting a transmission signal by an IQ orthogonal down-converter.
Patent Documents 4 to 9 are pointed out as other documents where techniques similar to those in Patent Document 1 to 3 are described.
Patent Document 10 discloses a modulator including comparison means for detecting a carrier leakage of an orthogonal modulator and comparing the detected carrier leakage and a carrier leakage value that has been held at an immediately preceding time.
Further, Patent Document 11 discloses a distortion compensation circuit in which data at four points of (I, Q)=a(1, 0), b(0, 1), c(−1, 0), and d(0, 1) are used as test signals. In this circuit, from detection levels when those data are used, an orthogonality error, where the influence of a DC offset is suppressed, is detected, and compensation is thereby performed.
Patent Document 1:
JP Patent Kokai Publication No. JP-P-2002-252663A
Patent Document 2:
JP Patent Kokai Publication No. JP-A-08-213846
Patent Document 3:
JP Patent Kohyo Publication No. JP-A-09-504673
Patent Document 4:
JP Patent Kokai Publication No. JP-P-2004-007083A
Patent Document 5:
JP Patent Kohyou Publication No. JP-P-2004-509555A
Patent Document 6:
International Publication No. WO2003/101061
Patent Document 7:
JP Patent No. 3037025
Patent Document 8:
JP Patent Kokai Publication No. JP-P-2004-274288A
Patent Document 9:
JP Patent Kokai Publication No. JP-P-2004-363757A
Patent Document 10:
JP Patent Kokai Publication No. JP-A-05-022356
Patent Document 11:
JP Patent Kokai Publication No. JP-A-11-136302